The present invention relates to a method of comparing data signals which are asynchronous.
It is important to be able to compare the content of data signals acquired asynchronously. For example, a logic analyzer acquires a first data signal from a standard instrument and stores it in a reference memory. Thereafter, the logic analyzer acquires a second data signal from another signal source and stores the acquired data in an acquisition memory. The data stored in the acquisition memory is compared with the data in the reference memory e.g., for checking the operation of the instrument providing the second data signal. Often, when acquiring these data signals, a trigger circuit of the logic analyzer compares the input data or some other signal being monitored with a reference data pattern. When the reference data pattern occurs, this trigger circuit generates a trigger pulse to stop storing the input data. A comparison can now be made with the previously stored data.
When the logic data is acquired asynchronously, although the two data may be the same, the acquired data can appear differently because of sampling clock skew, slight variations in delays or timing, or the like. Even if the sampling clock frequencies are higher that the data rate, the above-described problem may not be solved because of the changes in the data placement relative to the sampling clock. One of these conditions is shown in FIG. 1, wherein a data signal A is a single logic signal train, and pulses B and C are asynchronous sampling clocks. The clocks B and C have the same frequency; however, the phases thereof are different from each other because the clock signals B and C are not synchronized with the logic signal A. Data signals D and E illustrate the sampled data with the clock signals B and C, respectively. The data signal D is obtained as described hereinafter. When the clock signal B occurs at a time t.sub.2, the logic signal A is "Low" and therefore the analyzer stores the data as a "0". Since more than one transition has occurred between the times t.sub.2 and t.sub.3, the acquired data at the time t.sub.3 is a glitch (G) which is a pulse narrower than the sampling clock period. One transition has occurred between the times t.sub.3 and t.sub.4, and the logic level of the signal A is "High" at the time t.sub.4, so that the acquired data is "1". The similar operations are repeated, and thereby obtaining the data "0G1G0G1001" as the data signal D at the times t.sub.2 through t.sub.8. Similarly, the data E is "01G01G0101" acquired times t.sub.1 through t.sub.7. It should be noted that the data signal D is different from the data signal E, however, the logic signal A is common for the clock signals B and C. It should be noted that the sampling frequency is higher than the frequency of signal A between the times t.sub.5 and t.sub.8. The data signal D acquired at the times t.sub.6 through t.sub.8 is "1001", but the data signal E acquired at the t.sub.5 through t.sub.7 is "0101". These errors are commonly called aliasing errors. Prior techniques were unsuccessful in easily resolving comparison errors due to aliasing errors due to the asynchronous timebase.